module regfile (
	input wire clk,
	input [4:0] addr_a,
	input [4:0] addr_b,
	input [4:0] addr_d,
	input [31:0] data_d,
	input reg_w_en,

	output [31:0] data_a,
	output [31:0] data_b
);

    reg [31:0] registers[31:0];
	integer i;

	initial begin
		registers[0] <= 0;
		for (i = 1; i <= 32; i = i + 1)
		    begin
                registers[i] <= 0;
		    end
	end

    // read
	assign data_a = (addr_a==5'b0) ? 32'b0 : registers[addr_a];
	assign data_b = (addr_b==5'b0) ? 32'b0 : registers[addr_b];

    // write
	always @ (negedge clk) begin
		if (reg_w_en) begin
			registers[addr_d] <= data_d;
		end
	end
	

endmodule